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INTEGRATED CIRCUITS
FBL2040 3.3V BTL8-bit TTL to BTL transceiver
Product specification IC23 Data Handbook 1998 Dec 07
Philips Semiconductors
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
FEATURES
* 3.3V version of FB2040A with 70% power savings * 8-bit BTL transceivers * Separate I/O on TTL A-port * Inverting * Drives heavily loaded backplanes with equivalent load
impedances down to 10.
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Controlled output ramp and multiple GND pins minimize ground
bounce
* High drive 100mA BTL open collector drivers on B-port * Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Each BTL driver has a dedicated Bus GND for a signal return * Glitch-free power up/power down operation * Low ICC current * Tight output skew * Supports live insertion * Pins for the optional JTAG boundary scan function are provided * High density packaging in plastic Quad Flat Pack
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL Propagation delay AIn to Bn Propagation delay Bn to AOn Output capacitance (B0 - B7 only) Output current (B0 - B7 only) Standby AIn to Bn (outputs Low ) ICC Supply current Bn to AOn (outputs Low) AIn to Bn (outputs High) Bn to AOn (outputs High) PARAMETER TYPICAL 4.4 3.1 3.4 3.2 4 100 4 8 18 13 16 mA UNIT ns ns pF mA
ORDERING INFORMATION
PACKAGES 52-pin Plastic Quad Flat Pack (QFP) COMMERCIAL RANGE VCC = 3V10%; Tamb = -40C to +85C FBL2040BB DRAWING NUMBER SOT379-1
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IO OUT Tamb TSTG 1998 Dec 07 Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature 2 A0 - A7 B0 - B7 AI0 - AI7, OEB0, OEB1, OEA B0 - B7 PARAMETER RATING -0.5 to +4.6 -0.5 to +7.0 -0.5 to +3.5 -18 to +5.0 -0.5 to +7.0 64, -64 200 -40 to +85 -65 to +150 UNIT V V mA V mA C C 853-2136 20492
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
PIN CONFIGURATION
TCK (option) LOGIC VCC TMS (option) BUS GND BUS VCC BIAS V
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND AI1 AI2 AO2 LOGIC GND AO3 LOGIC GND AI3 AI4 AO4 LOGIC GND AO5 LOGIC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 BG VCC LOGIC GND TDO (option) TDI (option) BUS VCC BG GND AI5 AO6 AI6 AO7 AI7 NC B7 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
8-Bit Transceiver FBL2040 52-lead PQFP
B0/B0 35 34 33 32 31 30 29 28 27
OEB0
OEB1
AO1
AO0
AI0
OEA
SG00089
DESCRIPTION
The FBL2040 is an 8-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FBL2040 is an inverting transceiver. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEA goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEA goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 1.3V. The B-port has two output enables, OEB0 and OEB1. When OEB0 is High and OEB1 is Low the output is enabled. When OEB0 is Low
or if OEB1 is High, the B-port is inactive and is at the level of the backplane signal. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while VCC is Low. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. JTAG boundary scan pins are provided with signals TMS, TCK, TDI and TDO. TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. Boundary scan functionality is not implemented at this time.
1998 Dec 07
3
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
PIN DESCRIPTION
SYMBOL AI0 - AI7 AO0 - AO7 B0 - B7 OEB0 OEB1 OEA BUS GND LOGIC GND BUS VCC LOGIC VCC BG VCC BG GND BIAS V TMS TCK TDI TDO NC PIN NUMBER 51, 2, 3, 8, 9, 14, 18, 24 50, 52, 4, 6, 10, 12, 16, 20 40, 38, 36, 34, 32, 30, 28, 26 46 45 47 41, 39, 37, 35, 33, 31, 29, 27 1, 5, 7, 11, 13, 15 23, 43 49 17 19 48 42 44 22 21 25 TYPE Input Output I/O Input Input Input GND GND Power Power Power GND Power Input Input Input Output NC Data inputs (TTL) 3-state outputs (TTL) Data inputs/Open Collector outputs. High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the A outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Positive supply voltage Band Gap threshold voltage reference Band Gap threshold voltage reference ground Live insertion pre-bias pin Test Mode Select (optional, if not implemented then no-connect) Test Clock (optional, if not implemented then no-connect) Test Data In (optional, if not implemented then shorted to TDO) Test Data Out (optional, if not implemented then shorted to TDI) No Connect NAME AND FUNCTION
FUNCTION TABLE
MODE INPUTS AIn L AIn to Bn H L H Disable Bn outputs out uts X X X Bn to AOn X X X Disable AOn outputs H** = B* = -- Bn* -- -- -- -- X X L H L H X OEB0 H H H H L X L X X L X OEB1 L L L L X H X H H X X OEA L L H H X X H H H H L Z Z L H X X H L H L Z OUTPUTS AOn Bn* H** L H** L H** H** Input Input Input Input X
Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
1998 Dec 07
4
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL COB Tamb Supply voltage High-level in ut voltage input Low-level in ut voltage input Input clamp current High-level output current Low-level out ut current output Output capacitance on B port Operating free-air temperature range -40 AO0 - AO7 AO0 - AO7 B0 - B7 6 Except B0-B7 B0 - B7 Except B0-B7 B0 - B7 PARAMETER LIMITS MIN 3.0 2.0 1.62 1.55 0.8 1.47 -18 -32 32 100 7 +85 NOM 3.3 MAX 3.6 UNIT V V V mA mA mA pF C
LIVE INSERTION SPECIFICATIONS
SYMBOL VBIASV IBIASV S VBn ILM IHM IBnPEAK IO OFF OL tGR Bias pin voltage Bias pin ( BIASV) input (I DC current Bus voltage during prebias Fall current during prebias Rise current during prebias Peak bus current during insertion Power up current Input glitch rejection PARAMETER Voltage difference between the Bias voltage and VCC after the PCB is plugged in. VCC = 0 V, Bias V = 3.6V VCC = 3.3V, Bias V = 3.6V B0 - B8 = 0V, Bias V = 3.3V B0 - B8 = 2V, Bias V = 1.3 to 2.5V B0 - B8 = 1V, Bias V = 3 to 3.6V VCC = 0 to 3.3V, B0 - B8 = 0 to 2.0V, Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns VCC = 0 to 3.3V, OEB0 = 0.8V VCC = 0 to 1.2V, OEB0 = 0 to 5V VCC = 3.3V 1.0 1.35 -1 10 100 100 1.62 LIMITS MIN - TYP - MAX 0.5 1.2 10 2.1 1 UNIT V mA A V A A mA A ns
1998 Dec 07
5
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
LOGIC DIAGRAM FOR FBL2040
OEB0 46
OEB1 OEA AI0 AO0
45
47 40 51 50 B0
38 AI1 AO1 2 52
B1
36 AI2 AO2 3 4
B2
34 AI3 8 6
B3
TTL Levels
AO3
BTL Levels
32 B4
AI4 AO4
9 10
30 AI5 AO5 14 12
B5
28 AI6 AO6 18 16
B6
26 AI7 AO7 24 20
B7
TMS TCK TDI TDO NC = LOGIC VCC = LOGIC GND = = BUS VCC BUS GND = BIAS V = = BG VCC BG GND =
42 44 22 21
(Future JTAG Boundary Scan option)
25 49 1, 5, 7, 11, 13, 15 23, 43 27, 29, 31, 33, 35, 37, 39, 41 48 17 19
SG00077
1998 Dec 07
6
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. symbol IOH IO OFF parameter High level output current Power-off Power off output current B0 - B7 B0 - B7 test conditions1 VCC = MAX, VIL = MAX, VOH = 1.9V VCC = 0V, VIL = MAX, VOH = 1.9V VCC = 0V, VIL = MAX, VOH = 1.9V@85C VCC = MIN to MAX; IOH = -100A AO0 - AO73 VCC = MIN; IOH = -8mA VCC = MIN; IOH = -32mA VOL Low-level output voltage AO0 - AO73 B0 - B7 VIK Input clamp voltage Control pins II g Input leakage current Control/ AI0 - AI7 AI0 - AI7 Note 4 IIH IIL IOZH IOZL ICCZ ICCH ICCL ICCH ICCL High-level input current B0 - B7 VCC = MIN; IOL = 16mA VCC = MIN; IOL = 32mA VCC = MIN, IOL = 4mA VCC = MIN, IOL = 100mA VCC = MIN, II = IIK = -18mA VCC = 3.6V; VI = VCC or 100mV VCC = 0V or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 100mV VCC = MAX, VI = 1 9V MAX 1.9V VCC = MAX, VI = 3.5V, note 5 VCC = MAX, VI = 3.75V, Note 5 @ -40C Low-level Low level input current Off-state output current Off-state output current Supply current Supply current (total) Su ly BA B0 - B7 AO0 - AO7 AO0 - AO7 VCC = MAX, VI = 0.75V MAX 0 75V VCC = MAX, VO =3V VCC = MAX, VO = 0.5V VCC = MAX, outputs disabled, VI = GND or 0.0 VCC = MAX, outputs High, VI = GND or 0.0 VCC = MAX, outputs Low, VI = GND or 0.0 VCC = MAX, outputs High, VI = GND or 0.0 VCC = MAX, outputs Low, VI = GND or 0.0 16 16 18 13 8 100 100 -100 100 5 -5 31 35 39 30 16 mA 0.5 0.75 1.0 -0.85 1.20 -1.2 1.0 10 1 -5 100 A mA A A A A VCC -0.2 2.4 2.0 0.4 0.5 limits min typ2 max 100 100 300 unit A A V V V V V V V
VOH
High level out ut High-level output voltage
Su ly Supply current (total)
AB
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 3.3V, TA = 25C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Unused pins are at VCC or GND. 5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit is Active). This is not a tested condition.
1998 Dec 07
7
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 3.3V, RL = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(O) tSK(P) Propagation delay, AIn to Bn OEB0 to Bn OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between receivers in same package Pulse skew |tPHL - tPLH| MAX 1.0 1.2 1.4 2.0 1.5 1.4 1.0 1.2 0.5 0.3 TYP 2.7 3.0 3.1 4.1 3.3 3.2 1.7 1.9 1.0 1.0 MAX 5.7 5.1 5.0 6.4 5.3 5.0 2.5 2.5 Tamb = -40 to +85C, VCC = 3.3V10%, RL = 9 MIN 1.0 1.0 1.0 1.9 1.0 1.1 0.5 0.5 MAX 6.3 5.6 6.1 6.9 6.0 5.8 3.0 3.0 1.5 1.5 ns ns ns ns ns ns UNIT
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 3.3V, RL = 16.5 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(O) tSK(P) Propagation delay, AIn to Bn OEB0 to Bn OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between receivers in same package Pulse skew |tPHL - tPLH| MAX 1.2 1.2 1.8 1.8 1.6 1.3 1.0 1.2 0.5 0.3 TYP 2.8 2.8 3.6 3.8 3.4 3.0 1.7 1.9 1.0 1.0 MAX 4.4 4.6 5.6 5.9 6.2 4.8 2.5 2.5 Tamb = -40 to +85C, VCC = 3.3V10%, RL = 16.5 MIN 1.0 1.1 1.2 1.7 1.0 1.0 0.5 0.5 MAX 5.2 5.1 6.5 6.3 6.0 5.6 3.0 3.0 1.5 1.5 ns ns ns ns ns ns UNIT
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(O) tSK(P) PARAMETER Propagation delay, Bn to AOn OEA to AOn OEA to AOn Transition time, AOn Port (10% to 90% or 90% to 10%) Output skew between receivers in same package Pulse skew |tPHL - tPLH| MAX TEST CONDITION Tamb = +25C, VCC = 3.3V MIN 1.5 1.7 2.1 2.0 2.0 1.0 1.3 1.7 0.5 0.3 TYP 3.4 3.6 4.0 3.7 1.8 1.0 2.2 2.6 1.0 1.0 MAX 5.4 5.5 5.9 5.5 5.9 4.3 2.5 2.5 Tamb = -40 to +85C, VCC = 3.3V10% MIN 1.3 1.5 1.9 1.4 1.8 1.0 0.9 0.8 MAX 6.1 6.8 6.5 6.5 6.2 4.8 3.0 3.0 1.5 1.5 ns ns ns ns ns ns UNIT
1998 Dec 07
8
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
AC WAVEFORMS
AIn, Bn OEB1 VM tPLH VM VM tPHL VM AOn, Bn AIn, Bn OEB0 VM tPHL VM VM tPLH VM
AOn, Bn
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 2. Propagation Delay for Data or Output Enable to Output
AIn, Bn
VM tSK(o)
AOn, Bn
VM
Waveform 3. Output Skews
OEA VM tPZH AOn VM VM tPHZ VOH -0.3V OV AOn OEA VM tPZL VM VM tPLZ VOL +0.3V
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
SG00078
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others.
1998 Dec 07
9
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
TEST CIRCUIT AND WAVEFORMS
VCC BIAS V RL 7.0V NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10% LOW V tTLH VIN
90%
VIN PULSE GENERATOR RT D.U.T.
VOUT
(tf) (tr)
90% VM tW
(tr) (tf)
VIN
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open Family FB+
VCC BIAS V 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
Input Pulse Definitions
INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.5ns
A Port B Port
500ns 2.5ns 500ns 2.5ns
VIN PULSE GENERATOR RT D.U.T.
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00059
1998 Dec 07
10
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL TO BTL transceiver
74FBL2040
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
1998 Dec 07
11
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL TO BTL transceiver
74FBL2040
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04973
Philips Semiconductors
1998 Dec 07 12

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